1. Field of the Invention
The present invention relates to a technique for controlling semiconductor memory of a synchronous transfer system.
2. Description of the Related Art
A burst transfer for raising a transfer speed by partially eliminating procedures such as specifying an address is one of effective means for improving a data transfer rate of semiconductor memory when transferring continuous data synchronously with a clock signal.
For instance, a patent document 1 (Laid-Open Japanese Patent Application Publication No. 10-199233) has disclosed a method for implementing a burst transfer for EDO (extended data out) memory, which primarily performs an asynchronous transfer, by using a signal used for the EDO memory.
Synchronous DRAM (SDRAM), i.e., generic DRAM, operates when a BL (Burst Length) as one of setup values used for a burst transfer is equal to or greater than two for example, and a value of the BL can be controlled by a Mode Register Set (MRS) command.
Since control commands such as the MRS command can be input at a discretionary clock, a user is required to utilize SDRAM with an appropriate attention under various limitations such as timing. For example, the user is required to use it by considering a limitation of intervals when continuously accessing the same bank, that of intervals for being able to input an RD (Read) command from an active command, et cetera.
Incidentally, for a setup value BL, the present specification defines that the case of inputting and outputting data for the duration of N clocks by one RD (Read)/WT (Write) command is BL=N.
A memory controller managing a control of memory is required to control SDRAM so as to satisfy various constraint conditions, making its design difficult.
Meanwhile, if a design is tried by describing such a specification by a hardware description language such as Verilog and VHDL (VHSIC (very high speed integrated circuit) description language), a description content becomes complex due to a cumbersomeness of the control. Because of this, not only the description per se is difficult, but also an identification of the description with a specification is difficult to validate. Therefore, adoption of the specification as a logic mixed memory macro levies great loads on both a macro designer (i.e., a describer of Verilog/VHDL) and a macro user.